A 200-MS/s 10-Bit SAR ADC Applied in WLAN Systems

This paper introduces a new high-performance successive approximation register (SAR) analog-to-digital converter (ADC) designed for high-speed and low-power wireless local area network (WLAN) applications using SMIC 55 nm 1p8m CMOS process. The design employs several innovative techniques, including an improved bootstrap switch with high linearity, 4-reference voltage method to minimize capacitive digital-to-analog (CDAC) mismatch, kickback-canceling comparator eliminate kick-back noise, redundant design-assisted window-opening SAR logic decrease conversion time. Experimental results reveal that the proposed ADC achieves impressive signal-to-noise distortion ratio (SNDR) of 55.3 dB spurious-free dynamic range (SFDR) 66.6 at sampling rate 200 MHz Nyquist frequency input while consuming power 2.8 mW 1.2 V supply. corresponds figure-of-merit (FoM) value 29 fJ/conversion-step. Thanks incorporation method, demonstrates significant advantage compared other designs similar FOM values utilizing more advanced processes, occupying mere 0.008 mm2 core area.